In most real signal transmission applications there can be several sources of noise and distortions between the source of the signal and its receiver. As a result, there is a strong need to correct mistakes in the received signal. As a solution for this task one should use some coding technique with adding some additional information (i.e., additional bits to the source signal) to ensure correcting errors in the output distorted signal and decoding it. One type of coding technique utilizes low-density parity-check (LDPC) codes. LDPC codes are used because of their fast decoding (linearly depending on codeword length) property.
Iterative decoding algorithms allows a high degree of parallelism in processing, favoring the design of high throughput architectures of the related decoder. However, routing congestion and memory collision might limit a practical exploitation of the inherent parallelism a decoding algorithm. In order to solve this problem, codes are designed with a block structure (having blocks of size P) that naturally fit with the vectorization of the decoder architecture, thus guaranteeing a collision-free parallelism of P.
Joint code-decoder design techniques and the possibility of vectorizing the decoder architecture permit a reduction in the iteration latency, because P processing units work in parallel. Consequently, higher throughputs can be achieved with decoder architectures using more than P processing units in parallel; but because of the memory collision problem, the complexity overhead (or even the latency overhead in such processing that cannot be done in parallel) can be significant.
Consequently, it would be advantageous if an apparatus existed that is suitable for efficiently decoding LDPC code words in a layered architecture.